Currently in the market there exist manufacturers of serial memory devices that include a communication bus interface. For example, a manufacturer may incorporate a serial memory device with either an Inter-Integrated Circuit (I2C) communication bus interface or a Serial Peripheral Interface (SPI) bus, wherein each interface has a different pin count. Given this situation, conventionally suppliers of serial memories maintain and sell a different serial memory for each interface. For instance, the conventionally suppliers of serial memories can have one part number for an I2C interface serial memory and another part number for a Serial Peripheral Interface memory. Unfortunately, this leads to inventory issues as many different serial memories are maintained, supported, and the like.
One conventional solution for the above problem is to manufacture a single chip that includes, for example, both a Serial Peripheral Interface and an I2C interface and on the die itself are included six pads (two pads for the I2C interface and four pads for the Serial Peripheral Interface) to compensate for the difference in pin counts of the different interfaces. As such, if a manufacturer is going sell the single chip as an I2C interface serial memory, the manufacturer can bond out the two unique I2C pads to two pins on the package so that it can be used for I2C. Alternatively, if the manufacturer is going sell the single chip as a Serial Peripheral Interface serial memory, the manufacturer can bond out the four unique SPI pads to four pins on the package so that is can be used for SPI. However, one of the disadvantageous of including additional pads on the die to support the different memory interfaces is that it increases the manufacturing cost of the memory chip.
As such, it is desirable to address one or more of the above issues.